1. Field of the Invention
The present invention relates to a clock generation technique and, in particular, to a spread spectrum clock generator (abbreviated by SSCG), a semiconductor device equipped with the clock generator, and a clock generating method.
2. Description of the Related Art
In recent years, measures for electro-magnetic interference (EMI) have becomes more important along with improvement in operating frequency of a semiconductor device such as a large scale integrated circuit (LSI) and the like. A large number of printers, personal computers, and digital consumer electronic appliances, for example, is provided with a spread spectrum clock generator (SSCG) as measures for EMI. Since the internal clock signal of the LSI has a specific frequency, the spectrum of the clock has a peak in the specific frequency, which causes an electromagnetic radiation noise. The SSCG oscillates with the frequency of a clock slightly varied (frequency-modulated) to spread the energy of a spectrum into other frequencies, lowering the peak value in the specific frequency. A triangular waveform or a Hershey-kiss modulation waveform is often used for the modulation of frequency of a voltage controlled oscillator (VCO) whose oscillation frequency is varied by an applied control voltage.
FIG. 10 shows a Hershey-kiss waveform being a modulation waveform of the SSCG (FIG. 10 refers to FIG. 4 in Patent Document 1 in its entirety). In FIG. 10, an abscissa indicates the percentage of a period and an ordinate indicates the percentage of modulation deviation.
As discussed in Patent Document 1, a modulation circuit using the Hershey-kiss waveform adopts:
1) a method of changing the division ratio of a programmable counter in a feedback loop of a phase locked loop (PLL);
2) a method of generating a modulation waveform in an analog area; and
3) a method of inputting a digital code of a desired modulation waveform into a digital to analog converter
FIG. 11 shows a configuration for changing the division ratio of the programmable counter in the feedback loop of the PLL (FIG. 11 refers to FIG. 6 in Patent Document 1 in its entirety). The PLL in FIG. 11 includes a programmable counter 35 on the side of reference clock and a programmable counter 42 on the side of a feedback loop. Their respective division ratios are set by lookup tables 46 and 47. The division ratios of the programmable counters 35 and 42 are changed during the operation of PLL, to spread the spectrum of output clock signal of a VCO 39. A Y1 (31) denotes a piezo crystal element used in an oscillation circuit (OSC) 33.
FIG. 12 shows a configuration for generating a modulation waveform in an analog area (FIG. 12 refers to FIG. 7 in Patent Document 1 in its entirety). An analog modulation circuit 52 generates a modulation waveform and adds the modulation waveform to the control voltage of a VCO 51 to spread the spectrum of output clock of the VCO 51.
The analog modulation circuit 52 triples the outputs of a triangular waveform generation unit and a log amplifier which are not shown and causes the tripled outputs to pass through an anti-log circuit to obtain the characteristic of cube of the Hershey-kiss. A phase detector 37, a filter 38, a VCO 39, and a programmable counter 42 form the loop of a PLL. A voltage in which the modulation waveform from the analog modulation circuit 52 is added to the control voltage input to the VCO 39 is applied to the VCO 51 for output, and output via a buffer 40.
FIG. 13 refers to FIG. 8 in Patent Document 1 in its entirety. An oscillation circuit 72 and an inverter 71 generate a clock signal. A clock signal in which the output of the inverter 71 is divided by a programmable counter 35 is input to the phase detector 37 in the PLL (the loop of the phase detector 37, the filter 38, the VCO 39, and the programmable counter 42) as a reference clock. The oscillation circuit 72 includes a variable capacity element (varactor diode D). The capacitance of the varactor diode D is varied with the output voltage of the analog modulation circuit 52. The capacitance of the varactor diode D is varied to vary the oscillation frequency of the oscillation circuit 72, thereby spreading the spectrum of output clock from the PLL. The analog modulation circuit 52 is similar to that in FIG. 12 in configuration.
FIG. 14 refers to FIG. 9 in Patent Document 1 in its entirety and shows an example in which a desired waveform of a digital code is input to a digital to analog converter (DAC) 83 and the output thereof is used. The desired digital code is input to the digital to analog converter 83 from a read only memory (ROM) 82. The digital to analog converter 83 generates an analog modulation waveform and adds the analog modulation waveform to the control voltage of the VCO 51 to spread the spectrum of output clock of the VCO 51.    [Patent Document 1] U.S. Pat. No. 5,488,627    [Patent Document 2] U.S. Pat. No. 4,278,839